Tone inversion with partial underlayer etch for semiconductor device formation

ABSTRACT

A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.12/952,248, filed on Nov. 23, 2010, which is herein incorporated byreference in its entirety.

FIELD

This disclosure relates generally to the field of integrated circuit(IC) processing, and more specifically to tone inversion in ICprocessing and patterning.

DESCRIPTION OF RELATED ART

The manufacturing of semiconductor devices is dependent upon theaccurate replication of computer aided design (CAD) generated patternsonto the surface of the device substrate. The replication process istypically performed using lithographic processes, followed by a varietyof subtractive (etch) and additive (deposition) processes. Moreparticularly, a photolithography process typically includes applying alayer of photoresist material (i.e., a material that will react whenexposed to light), and then selectively exposing portions of thephotoresist to light or other ionizing radiation (e.g., ultraviolet,electron beams, X-rays, etc.), thereby changing the solubility ofportions of the material. The resist is then developed by washing itwith a developer solution, such as tetramethylammonium hydroxide (TMAH),thereby removing the non-irradiated (in a negative resist) or irradiated(in a positive resist) portions of the resist layer.

In the fabrication of complementary metal-oxide-semiconductor (CMOS)devices, several implant masks may be used to form appropriate sourceand drain areas on a chip. For p-type and n-type CMOS field effecttransistor devices (NFETs and PFETs), some of the patters arecomplementary; that is, the pattern used for creating the p-type devicesis the reverse of the pattern used for creating the n-type devices. Morespecifically, two separate masks are used in CMOS device processing inwhich either a positive or a negative resist is used to carry out twoseparate, complementary masking and implanting steps. For example, afirst implant is formed by creating a first patterned (positive ornegative) photoresist layer over a substrate. A first ion implantationis used to implant the exposed areas of the substrate with a firstdopant material (e.g., a p-type material). Subsequently, the firstpatterned layer is stripped and a second patterned resist (of the sametone as the first resist) is used to expose the complementary regions ofthe substrate regions in order to carry out the complementaryimplantation with a second dopant material (e.g., an n-type material).

However, as devices become more miniaturized, the conventional methodsfor complementary device implantation are more susceptible to alignmenterrors as a result of the separate masking steps. Such alignment errorswould limit the density and performance of the resulting devices. Thesealignment errors may include rotation errors, translation errors,overlap errors, and/or image size deviations. In turn, the possibilityof incurring one or more of these errors results in the increase of theoverall device error placement budget, thereby reducing valuable chipreal estate that would otherwise be used for additional devices.

An image reversal process is a technique used in CMOS device processing,in which a combination of positive and negative resists is used for suchsteps as gate/line patterning or contact hole patterning. In oneapproach, a positive photoresist layer formed over a substrate ispatterned to create an opening for a gate pattern or a line pattern.Subsequently, a negative resist is formed over the irradiated positivephotoresist, including the formed opening. Then, the negative resist isrecessed such that it remains open only in the area defined by theopening formed in the positive resist layer, while the remainingpositive resist is removed. The remaining hardened negative resistdefines the location for the gate or line pattern.

Although this type of image reversal process may be used to form certaintypes of semiconductor structures, it is not particularly suited for thetype of complementary implant regions discussed above, due tointermixing between negative and positive photoresists duringapplication. The intermixing may cause deformation of the underlyingfirst resist pattern, impacting line width control and causing residualresist defects. Moreover, even if this approach were able to be adaptedfor complementary device implantation, there are still two separatelithography steps needed in accomplishing the image reversal.

Another existing approach is to utilize spun-on glass (SOG) overphotoresist for image reversal purposes. However, SOG is an oxidematerial that is typically removed using harsh solvents such as diluteor buffered hydrofluoric acid (HF), which tends to cause damage to theother oxide layers on the device substrate.

A significant part of the cost of an integrated circuit chip iscontained in the lithography processes used to pattern the implant masklevels, especially at relatively small dimensions. As such it isdesirable to be able to implement image reversal for applications suchas CMOS device implantation, but without the added lithography stepsneeded heretofore, or the risk of device damage from removing SOG, toaccomplish the image reversal.

SUMMARY

In one aspect, a structure for tone inversion for integrated circuitfabrication includes a substrate; a partially etched underlayercomprising a first pattern located over the substrate, the first patternbeing partially etched into a portion of the underlayer such that aremaining portion of the underlayer is protected and forms a secondpattern, and such that the first pattern does not expose the substratelocated underneath the underlayer; and an image reversal material (IRM)layer located over the partially etched underlayer.

Additional features are realized through the techniques of the presentexemplary embodiment. Other embodiments are described in detail hereinand are considered a part of what is claimed. For a better understandingof the features of the exemplary embodiment, refer to the descriptionand to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alikein the several FIGURES:

FIG. 1 illustrates an embodiment of a method for tone inversion withpartial underlayer etch.

FIG. 2 illustrates an embodiment of a starting substrate afterapplication and patterning of photoresist.

FIG. 3 illustrates an embodiment of the device of FIG. 2 after partialetching of the underlayer and removing the photoresist.

FIG. 4 illustrates an embodiment of the device of FIG. 3 after formationof an image reverse material layer over an antireflective coating layerand the partially etched underlayer.

FIG. 5 illustrates an embodiment of the device of FIG. 3 after removalof an antireflective coating layer and formation of an image reversalmaterial layer over the partially etched underlayer.

FIG. 6 illustrates an embodiment of either the devices of FIG. 4 or 5after etchback of the image reverse material layer.

FIG. 7 illustrates an embodiment of the device of FIG. 6 after etchingthe underlayer down to the hardmask layer.

FIG. 8 illustrates an embodiment of the device of FIG. 7 after etchingthe hardmask layer.

FIG. 9 illustrates an embodiment of the device of FIG. 8 after removalof the remaining image reverse material layer.

FIG. 10 illustrates an embodiment of the device of FIG. 9 after removalof the remaining underlayer.

DETAILED DESCRIPTION

Embodiments of a method for tone inversion with partial underlayer etchare provided, with exemplary embodiments being discussed below indetail. A technique for relatively small dimension pitch patterning andimage reversal is brightfield imaging with a tone inversion process.Tone inversion may involve two separate resist exposures to double thepitch in some embodiments, followed by application of an etch selective,tone inversion overcoat material, also referred to as an image reversematerial (IRM), which may be applied directly on patterned photoresistto transfer a brightfield image into the reverse tone. The IRM is thenetched back after application. However, a tone inversion process may besusceptible to large critical dimension (CD) variance, due to unevenresist application, resist profile, and varying resist height. Byincluding an underlayer under the resist, and performing a partial etchof the underlayer using the resist as a mask prior to application of theIRM, the resulting partially etched underlayer structure may berelatively square and uniform, and which may result in a uniform toneinversion etch step with low CD variance. The tone inversion process isalso made significantly more robust by use of the partial underlayeretch. Partial etching of the underlayer may also reduce or eliminates CDvariance in the finished IC that may result from photoresist sidewallprofile or resist height.

The tone inversion process may also include an antireflective coating(ARC) located over the underlayer. In some embodiments, the ARC may beleft intact during IRM application. However, with an intact ARC layer,the IRM etchback budget may be different in dense line regions of the ICversus in open areas, which may lead to punchthrough of the IRM duringetching and a limited IRM etchback process window. In other embodiments,the ARC may be fully or partially removed before application of the IRMcoating. Partial or full ARC removal may further enhance the processwindow for the IRM etchback.

FIG. 1 illustrates an embodiment of a method for tone inversion withpartial underlayer etch. FIG. 1 is discussed with reference to FIGS.2-11. In block 101, photoresist is applied to a surface of a startingsubstrate that includes a bottom dielectric 201, dielectric cap 202,hardmask layer 203, underlayer 204, and ARC 205, and the photoresist ispatterned, resulting in patterned photoresist 206 as shown in structure200 of FIG. 2. The bottom dielectric 201 may be any appropriatedielectric material. Dielectric cap 202 may include silicon oxide formedfrom a tetraethyl orthosilicate (TEOS) precursor in some embodiments,and may have a thickness from about 20 nanometers (nm) to about 200 nmin some embodiments. Hardmask 203 may include a metal such as titaniumnitride (TiN) or boron nitride (BN), or a metal oxide, and have athickness from about 20 nm to about 70 nm in some embodiments.Underlayer 204 may include an organic material such as a polymer in someembodiments, and may have a thickness from about 50 nm to about 400 nmin some embodiments. In some embodiments, underlayer 204 may include abottom layer of a first underlayer material, and a top layer of a secondunderlayer material; the interface between the two underlayer materialsmay act as an etch stop during the partial underlayer etch (discussedbelow with respect to block 102). ARC 205 acts to minimize the lightreflection during lithography, and also acts as a masking layer for thepartial etch of underlayer 204 in block 102. ARC 205 may include silicon(Si) in some embodiments, and may have a thickness from about 20 nm toabout 100 nm in some embodiments. The photoresist 206 may be anyappropriate type(s) of photoresist, and may be applied using anyappropriate method(s), depending on the device being formed. Thephotoresist 206 may be single, double, or triple patterned, and may havea thickness from about 30 nm to about 150 nm in various embodiments.Photoresist 206 may include an argon fluoride (ArF) single exposureresist, a double exposure resist (i.e. thermal cure system), or anextreme ultraviolet (EUV) resist formed by an optical process in variousembodiments.

In block 102, underlayer 204 is partially etched, with ARC layer 205acting as a mask during the partial etching, as shown in FIG. 3,resulting in etched underlayer 301 and bottom underlayer 302. Thepartial etch of underlayer 204 does not expose hardmask 203. Photoresistlayer 206 is also etched away during the partial etching of underlayer204. In some embodiments, etched underlayer 301 and bottom underlayer302 comprise the same material. In other embodiments in which underlayer204 includes a bottom layer of a first underlayer material and a toplayer of a second underlayer material, the bottom layer forms bottomunderlayer 302, and the top layer forms etched underlayer 301. The etchchemistry for the underlayer etch of block 102 is selective against thematerial comprising the bottom underlayer 302 in such an embodiment. Theinterface between the two underlayer materials may act as an etch stopduring the partial underlayer etching. The first underlayer may includean organic material such as a polymer in some embodiments; and thesecond underlayer may be a metal hardmask layer, such as TiN, with athickness ranging from a few nm to 50 nm, in some embodiments.

In block 103, an image reversal material (IRM) layer 401 is formed overthe partially etched underlayer 301/302. The IRM layer 401 may be formedby spin-coating, and include any material that is etch selective to thematerial(s) comprising partially etched underlayer 301/302. In someembodiments, the IRM layer 401 may be a silicon-containing overcoatlayer, which may comprise (but is not limited to) a silicon-containingpolymer. The polymer may be a siloxane, silsesquioxane, hydrogensilsequioxane, or other related materials in various embodiments. Insome embodiments, the etched ARC 205 of FIG. 3 may not be removed, ormay be partially removed, before formation of IRM layer 401, as shown inFIG. 4. FIG. 4 illustrates an embodiment of the device of FIG. 3 afterpartial removal of ARC 205 and formation of IRM layer 401. In otherembodiments, the etched ARC 205 of FIG. 3 may be fully removed beforeformation of IRM layer 401, as shown in FIG. 5. FIG. 5 illustrates anembodiment of the device of FIG. 3 after full removal of ARC 205 andformation of IRM layer 401. Partial or full ARC removal beforeapplication of IRM layer 401 may decrease the likelihood of IRMpunchthrough in the open field region during the IRM etchback, which isdiscussed below with respect to block 104.

In block 104, etchback of IRM layer 401 is performed to expose the topof etched underlayer 301, as shown in FIG. 6. The etch of block 104 maybe a plasma etch, and may be selected such that the IRM 401 is etchedselective to the material that comprises partially etched underlayer301/302. In embodiments in which ARC 205 was fully removed beforeformation of IRM layer 401 (such as FIG. 5), only etchback of IRM layer401 is necessary in block 104. In embodiments in which ARC 205 is notremoved or partially removed before formation of IRM layer 401 (such asFIG. 4), any ARC 205 located on etched underlayer 301 is removed duringthe etchback of IRM layer 401 in block 104. In such an embodiment, boththe IRM 401 that is located above the etched underlayer 301 and the ARC205 need to be etched away in block 104 in order to reverse patterns inthe dense line region (indicated by line 602); however, in the openfield region (indicated by lines 601), only the IRM coating layer 401needs to be etched. Therefore, without full or partial removal of ARC205 in the dense line region 602 prior to etchback in block 104, therisk of punchthrough of IRM 401 in the open field region 601 during theetch of block 104, exposing bottom underlayer 302 or hardmask layer 203,may be increased.

Then, in block 105, the etched underlayer 301 and bottom underlayer 302are etched down to expose hardmask layer 203, resulting in structure 700as shown in FIG. 7. The etchedback IRM layer 401 acts as a mask duringthe etching of the partially etched underlayer 301/302 that is performedin block 105.

In block 106, the hardmask layer 203 is etched using bottom underlayer302 as a mask. The etch of hardmask layer 203 may include a breakthroughstep and an etching step in some embodiments. The breakthrough step mayinclude an oxide breakthrough plasma etch that may be used to punchthrough the oxidized top portion of hardmask layer 203 in someembodiments. After the breakthrough of hardmask 203 is completed,hardmask 203 is etched, resulting in structure 800 as shown in FIG. 8.IRM layer 401 is also removed in block 106. The IRM layer 401 may befully removed before hardmask layer 203 is etched, or the IRM layer 401may be thinned down before the etch of hardmask layer 203 in someembodiments, so that the thinned IRM layer 401 is removed during theetch of hardmask layer 203 in other embodiments.

After etching of hardmask layer 203 and removal of IRM layer 401 inblock 106, in block 107 the bottom underlayer 302 is removed, resultingin the structure shown in FIG. 9. Then, in block 108, the dielectric cap202 and dielectric layer 201 are etched with hardmask layer 203 actingas a mask, resulting in device 1000 shown in FIG. 10. The etcheddielectric layer 201 of device 1000 may then be used to fabricate ametal layer for an IC. To form a finished IC, any appropriate additionalprocessing may be performed using a device that is formed using method100 (such as device 1000), including back-end-of-line (BEOL) integrationfor metal interconnects, which may require via-trench dual damascenestructures. Method 100 may be integrated with any appropriate viaprocess schemes to form via-trench dual damascene structures that may beused to form metal interconnects.

The technical effects and benefits of exemplary embodiments includeprevention of IRM punchthrough during IRM etchback and increased CDuniformity in a finished IC.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A structure for tone inversion for integrated circuit fabrication,comprising: a substrate; a partially etched underlayer comprising afirst pattern located over the substrate, the first pattern beingpartially etched into a portion of the underlayer such that a remainingportion of the underlayer is protected and forms a second pattern, andsuch that the first pattern does not expose the substrate locatedunderneath the underlayer; and an image reversal material (IRM) layerlocated over the partially etched underlayer.
 2. The structure of claim1, wherein the IRM layer comprises a silicon-containing polymer.
 3. Thestructure of claim 1, wherein the underlayer comprises an organicmaterial.
 4. The structure of claim 1, wherein the underlayer comprisesa polymer.
 5. The structure of claim 1, wherein the partially etchedunderlayer comprises a top underlayer material layer over a bottomunderlayer material layer, and an interface between the top underlayermaterial layer and the bottom underlayer material layer is configured toact as an etch stop during the partial etching of the first pattern intounderlayer.
 6. The structure of claim 5, wherein the top underlayermaterial layer comprises a metal hardmask.
 7. The structure of claim 6,wherein the metal hardmask comprises titanium nitride.
 8. The structureof claim 5, wherein the bottom underlayer material layer comprises anorganic material.
 9. The structure of claim 5, wherein the bottomunderlayer material layer comprises a polymer.
 10. The structure ofclaim 1, wherein the substrate comprises a hardmask over a dielectriclayer, and wherein the partially etched underlayer is located on thehardmask.
 11. The structure of claim 10, wherein the hardmask comprisesa metal.
 12. The structure of claim 10, wherein the hardmask comprisesone of titanium nitride and boron nitride.